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PRELIMINARY
WMS7202
256-TAP DUAL-CHANNEL NON-VOLATILE DIGITAL POTENTIOMETER
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Publication Release Date: January 2003 Revision 1.1
WMS7202
1. GENERAL DESCRIPTION
The WMS7202 is a 256-tap, dual-channel non-volatile digital potentiometer available in 10K, 50K and 100K end-to-end resistances. These devices can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications. The output of each potentiometer is determined by the wiper position, which varies linearly between VA and VB terminal according to the content stored in the volatile Tap Register (TR). The settings of the TR can be provided either directly by the user through the industry standard SPI interface, or by the non-volatile memory (NVMEM0~3) where the previous settings are stored. When changes are made to the TR to establish a new wiper position, the value of the setting can be saved into any nonvolatile memory location (NVMEM0~3) by executing a NVMEM save operation. Each channel has its own four non-volatile memory locations (NVMEM0~3) that can be directly written to, and read by, users through the SPI interface. Upon powerup the content of the NVMEM0 is automatically loaded to the Tap Register. The WMS7202 contains two independent channels in 14-pin PDIP, SOIC and TSSOP packages and can operate over a wide operating voltage range from 2.7V to 5.5V. A selectable output buffer is builtin for each channel for those applications where an output buffer is required.
2. FEATURES
* * * * * * * * * * * * *
256 taps for each potentiometer Dual independent, linear-taper channels in one package End-to-end resistance available in 10K, 50K and 100K Selectable output buffer for each channel SPI Serial Interface for data transfer and potentiometer control Daisy-chain operation for multiple devices Nonvolatile storage of four wiper positions per channel with power-on recall from NVMEM0 Low standby current (1A Max. with output buffer inactive) Endurance 100K typical stores per bit Register Data Retention 100 years Industrial temperature range: -40 ~ 85C Wide operating voltage range: 2.7V ~ 5.5V Package option: 14-pin TSSOP, 14-pin SOIC, 14-pin PDIP
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WMS7202
3. BLOCK DIAGRAM
Serial Interface
Tap
CLK CS SDI SDO
Re Ta gi p st er
Register
De co de r
Decoder
VA1 MUX VW1 VB1
NVMEM0 (Non-volatile Memory 0; Power -on recall) NVMEM1 (Non-volatile Memory 1) NVMEM2 (Non-volatile Memory 2) NVMEM3 (Non-volatile Memory 3) WP Decoder Tap R/B NV Memory Control Re Ta gi p st er Register De co de r VA2 MUX VW2 VB2
VDD
NVMEM0 (Non-volatile Memory 0; Power-on recall) NVMEM1 (Non-volatile Memory 1) NVMEM2 (Non-volatile Memory 2) NVMEM3 (Non-volatile Memory 3)
VSS
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Publication Release Date: January 2003 Revision 1.1
WMS7202
4. TABLE OF CONTENTS
1. GENERAL DESCRIPTION.................................................................................................................. 2 2. FEATURES ......................................................................................................................................... 2 3. BLOCK DIAGRAM .............................................................................................................................. 3 4. TABLE OF CONTENTS ...................................................................................................................... 4 5. PIN CONFIGURATION ....................................................................................................................... 5 6. PIN DESCRIPTION ............................................................................................................................. 6 7. FUNCTIONAL DESCRIPTION............................................................................................................ 7 7.1. Potentiometer and Rheostat Modes ............................................................................................. 7 7.1.1. Rheostat Configuration .......................................................................................................... 7 7.1.2. Potentiometer Configuration .................................................................................................. 7 7.2. Programming Modes .................................................................................................................... 7 7.3. Non-Volatile Memory (NVMEM) ................................................................................................... 8 7.3.1 Write Protect of NVMEM ......................................................................................................... 8 7.4 Flow Control................................................................................................................................... 8 7.5. Daisy Chain .................................................................................................................................. 9 7.6. Serial Data Interface ................................................................................................................... 10 7.7. Instruction Set............................................................................................................................. 12 7.8. Basic Operation .......................................................................................................................... 12 7.8.1 Sending a Command ............................................................................................................ 12 7.8.2 Wake Up/Sleep/Power Commands ...................................................................................... 13 7.8.3 Write to Tap Register (TR).................................................................................................... 13 7.8.4 Programming Non-Volatile Memory (NVMEM)..................................................................... 14 7.8.5 Reading Tap Registers and NVMEM Locations ................................................................... 15 8. TIMING DIAGRAMS.......................................................................................................................... 16 9. Absolute Maximum Ratings............................................................................................................... 18 10. ELECTRICAL CHARACTERISTICS ............................................................................................... 19 10.1 Test Circuits............................................................................................................................... 21 11. TYPICAL APPLICATION CIRCUIT ................................................................................................. 22 11.1. Layout Considerations .............................................................................................................. 25 12. PACKAGE DRAWINGS AND DEMINSIONS.................................................................................. 26 13. ORDERING INFORMATION........................................................................................................... 29 14. VERSION HISTORY ....................................................................................................................... 30
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WMS7202
5. PIN CONFIGURATION
VDD SDO VA1 VW1 VB1 1 23 CS CLK SDI WP VSS 14 TSSOP
VDD SDO VA1
CS CLK SDI WP VSS R/B VA2
CS CLK SDI
14 PDIP
14 SOIC
WP VSS
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Publication Release Date: January 2003 Revision 1.1
R/B VA2
R/B VA2
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VDD SDO VA1 VW1 VB1 VB2 VW2
VW1 VB1
VB2 VW2
14 13 12 11 10 9 8
14 13 12 11 10 9 8
1 23
4 5 67
4 5 67
VB2 VW2
WMS7202
6. PIN DESCRIPTION
TABLE 1 - PIN DESCRIPTION PIN NAME CLK PIN NO 2 I/O I DESCRIPTION Serial Clock pin. Data Shifts in one bit at a time on positive clock (CLK) edges Chip Select pin. When CS is HIGH, WMS7202 is deselected and the SDO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. CS LOW enables WMS7202, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Serial Data Input pin. All opcodes, byte addresses and data to be written to the registers are input on this pin. Data is latched by the rising edge of the serial clock. Serial Data Output pin with open-drain output. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock except for the 1st bit , which is clocked out by the falling edge of CS. Also can be used to daisy-chain several parts. Ready signal with active-LOW, open-drain output, and acknowledges the completion of commands 2, 4, 5, 6, and 7. Hardware Write Protect pin. When active LOW WP prevents any changes to the present contents except retrieving NVMEM contents. Power Supply Ground pin, logic ground reference A terminal of potentiometer `1', equivalent to the HI terminal connection on a mechanical potentiometer B terminal of potentiometer `1', equivalent to the LO terminal connection on a mechanical potentiometer Wiper terminal of potentiometer `1', equivalent to the wiper terminal of a mechanical potentiometer A terminal of potentiometer `2', equivalent to the HI terminal connection on a mechanical potentiometer. B terminal of potentiometer `2', equivalent to the LO terminal connection on a mechanical potentiometer. Wiper terminal of potentiometer `2', equivalent to the wiper terminal of a mechanical potentiometer.
CS
1
I
3 SDI 13 SDO O I
R/B
6
O
WP
4 14 5 12 10 11 7 9 8
I O O
VDD VSS VA1 VB1 VW1 VA2 VB2 VW2
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WMS7202
7. FUNCTIONAL DESCRIPTION
The WMS7202 series, a family of 256-tap, nonvolatile digitally programmable potentiometers is designed to operate as both a potentiometer or a variable resistor depending upon the output configuration selected. The chip can store four 9-bit words in nonvolatile memory (NVMEM0 ~ NVMEM3) and the word stored in the NVMEM0 will be used to set the tap register values when the device is powered up. The WMS7202 is controlled by a serial SPI interface that allows setting tap register values as well as storing data in the nonvolatile memory. 7.1. POTENTIOMETER AND RHEOSTAT MODES The WMS7202 can operate as either a rheostat or as a potentiometer (voltage divider). When in the potentiometer configuration there are two possible modes. One is without the output buffer and the other mode is with the output buffer. Selecting the mode is done by controlling bit D8 of the data register. D8 = 0 sets the output buffer off and D8 = 1 sets it on. Each channel can be independently set to either buffer On or Off. Note that this bit can only be set by loading the value to the NVMEM with instructions #5 and then loading the TAP register with instruction #6 from NVMEM. This bit cannot be controlled by directly writing the value to the chip when the tap register is set. 7.1.1. Rheostat Configuration The WMS7202 acts as a two terminal resistive element in the rheostat configuration where one terminal is either one of the end point pins of the resistor (VA and VB) and the other terminal is the wiper (VW) pin. This configuration controls the resistance between the two terminals and the resistance can be adjusted by sending the corresponding tap register setting commands to the WMS7202 or loading a pre-set tap register value from nonvolatile memory NVMEM0 ~ MVMEM3. 7.1.2. Potentiometer Configuration In potentiometer configuration an input voltage is connected to one of the end point pins (VA or VB). The voltage on the wiper pin will be proportional to the voltage difference between VA and VB and the wiper setting. The resistance cannot be directly measured in this configuration. 7.2. PROGRAMMING MODES Two program modes are available for the WMS7202: * Direct program mode. The tap register setting can be changed either by loading a predetermined value from an external microcontroller or by using the UP/DOWN commands. The UP and DOWN commands change the tap register setting incrementally i.e., 1 LSB at a time. The UP and DOWN commands will not wrap around at the ends of the scale. NVMEM restore mode. One of the previously stored settings can be loaded into the TR register from the non-volatile memory. Four 9-bit non-volatile memories, are available for each channel to store tap register settings. The first register, NVMEM0, stores the favorite or default tap register setting that will be loaded into the tap register at system power up or software power on reset operation.
*
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Publication Release Date: January 2003 Revision 1.1
WMS7202
7.3. NON-VOLATILE MEMORY (NVMEM) Each channel has four NVMEM positions available for storing the output buffer operating mode and the potentiometer setting. These NVMEM positions can be directly written through the SPI using a write command (#5) with address and data bytes. Another command (#7) is available that stores the current output buffer operating mode and potentiometer settings into the selected NVMEM position. Bit A3 and A2 in the instruction byte decide which NVMEM position is used. (See Table 5) All potentiometers are loaded with the value stored in the NVMEM position 0 for their respective channel on power up. 7.3.1 Write Protect of NVMEM Write-protect ( WP ) disables any changes of current content in the NVMEM regardless of the commands, except that NVMEM setting can be retrieved using commands 4, 6 of Table 5. Therefore, Write-Protect ( WP ) pin provides hardware NVMEM protection feature with WP tied to Vss. WP , which is active at logic LOW, should be tied directly to VDD if it is not being used. 7.4 FLOW CONTROL Reading and writing to NVMEM requires an internal access cycle to complete before the next command can be sent. The following commands have additional flow control using the R/B pin. Read Tap Register (#2) Read NVMEM (#4) Program NVMEM (#5) Load Tap Register(#6) Program NVMEM with Tap Register (#7) The R/B bit will be pulled HIGH when CS goes LOW, and will stay HIGH indicating the chip is ready to accept another command. After sending one of those commands, the R/B pin should be polled to determine when the device is ready to accept the additional data. This flow control can be used on all commands without any performance penalty although it is only needed on the commands listed above.
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WMS7202
7.5. DAISY CHAIN Multiple devices can be controlled by the same bus without the need for extra CS lines from the microcontroller by daisy chaining the devices with the SDO of the first device connected to SDI of the next device as shown in figure 3 CS Micro controller CLK SDO CS CLK SDI SDO Device CS CLK SDI SDO Device CS CLK SDI SDO Device VDD
FIGURE 3 - DAISY CHAIN CONFIGURATION A complete command is 24 bits including the instruction and the two data bytes. When shifting 24 bits in to the first device in the chain, the 24 bits of the previous command will be shifted out. So to set up two devices in a daisy chain, a total of 48 bits must be sent where the first 24 bits will be shifted out to the second device and the 24 bits shifted in last will remain in the first device. 1. Command and data for device 2 is shifted into device 1; this will propagate to Device 2 when the next 24 bits are shifted in. Device Command 1 Data 2 Data 2
Device xx xx xx
2. Command and data for device 1 is shifted into device 1. Now Device 1 and 2 are correctly set up Device Command 2 Data 1 Data 1
Device Command A
Data
2
Data
2
FIGURE 4 - DAISY CHAIN COMMAND EXAMPLE
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Publication Release Date: January 2003 Revision 1.1
WMS7202
7.6. SERIAL DATA INTERFACE The WMS7202 contains a four-wire SPI interface: * * * SDO (Serial Data Output) Used for reading out the internal register contents and for daisy chaining multiple devices. SDI (Serial Data Input) Used for clocking in commands and potentiometer settings. CS (Chip Select) This pin must be pulled LOW before starting to send a command and pulled HIGH to signal the end of the command. This pin can be used to control multiple devices on the bus. CLK (Clock) The SDI bits are shifted in on the rising edge of the clock and SDO data is shifted out on the falling edge of the clock.
*
The key features of this interface include: * * * * * * Independently programmable Read & Write to all registers Direct parallel refresh of all Tap registers from corresponding internal NVMEM registers Increment and decrement instruction for each Tap register Nonvolatile storage of the present Tap register values into one of the four NVMEM registers available to each channel Configurable output buffer amplifier to allow both the functions of a potentiometer and a variable resistor Four 9-bit non-volatile registers store four preset wiper positions and the first one will be recalled to set the wiper position during power up.
The serial interface uses an SPI compatible uniform 24-bit word format as shown below. This format is used for all members of the WMS720x family. The data is sent MSB first. TABLE 2 - 24-BIT DATA WORD FORMAT
MSB C3 C2 C1 C0 A3 A2 A1 A0 X X X X X X X D8 D7 D6 D5 D4 D3 D2 D1 LSB D0
C3-C0 are the command bits that control the operation of the digital potentiometer according to the command instructions shown in the Instruction Set in Table 5 in Section 7.7. A1 and A0 are the address bits that determine which channel is activated, as shown in the table below. For the WMS7202 only the first two codes are used.
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WMS7202
TABLE 3 - A1 AND A0 ADDRESS BIT DECODE TABLE [A1 A0] Channel [0 0] 0 [0 1] 1 [1 0] 2 [1 1] 3
A3 and A2 are the address bits that decide which NVMEM memory to be accessed, as shown in the table below. TABLE 4 - A3 AND A2 ADDRESS BIT DECODE TABLE [A3 A2] NVMEM [0 0] 0 [0 1] 1 [1 0] 2 [1 1] 3
D7-D0 are the data values to be loaded into the Tap Register to set the wiper position, while D8 is used to set the output mode. D8 has to be loaded into the NVMEM0~3 first and then the "Load Tap Register" command (#6) has be executed to load D8 into the output-selection MUX to set the output mode. D8=0 sets the output to Buffer Off mode while D8=1 sets to Buffer On mode.
CS 1 CLK SDI
CS is taken LOW before command starts
CS is taken HIGH after command is sent
23
45
6
7
8
91 0 x
111 123 x x
1 4
111 567
11 89
2 0
22 12
22 34
C3 C2 C1 C0 A3 A2 A1 A0 x
xx
x D8 D7 D6 D5 D4 D3 D2 D1 D0
SDO SDI must be valid on the rising edge of the clock SDO is valid on the falling edge of the clock or CS R/B
Note: * * A multiple of 24 bits must always be sent or the command will not be valid Bits marked `x' are don't care bits.
R/B goes LOW at completion of commands 2, 4, 5, 6 and 7 to allow NVMEM to program for TSV. For other commands, R/B stays HIGH after command is sent.
FIGURE 5 - SPI COMMAND WAVEFORMS Publication Release Date: January 2003 Revision 1.1
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WMS7202
7.7. INSTRUCTION SET TABLE 5 - INSTRUCTION SET
Inst No. Instruction Byte C3 C2 C1 C0 A3 A2 A1 A0 0 1 0 1 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 xxxx x x A1 A0 x x A1 A0 Data Byte 1 D15 D14 D13 D12 D11 D10 D9 D8 x x x x x D8 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Data Byte 2 D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx xxxxxxxx D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx No Operation (NOP). Do nothing Read Tap Register and output selection MUX register Write to Tap Register with D7-D0 Read NVMEM pointed to by A3-A0 Program NVMEM pointed to by A3-A0 with D8-D0 Load Tap Register and output selection MUX register with the contents of NVMEM pointed to by A3-A0 Program NVMEM pointed to by A3-A0 with the contents of Tap Register and output selection MUX register Up: Increment setting of TR by one tap Down: Decrement setting of TR by one tap Sleep: Discontinue clock supply to the logic and memories Wake Up: Clock supply to the logic and memories Byte-erase NVMEM pointed to by A3-A0 Power On Reset: Software reset the part to the power up state Operation
1 2 3 4 5 6
0 A3 A2 A1 A0 0 A3 A2 A1 A0 1 A3 A2 A1 A0
7
0
0
1
1 A3 A2 A1 A0
x
x
x
x
x
x
x
x
xxxxxxxx
8 9 10 11 12 13
0 1 1 0 1 1
1 1 0 0 1 0
1 1 0 0 0 0
1 1 0 1
x x A1 A0 x x A1 A0 xxxx xxxx
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
x x x x x x
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
1 A3 A2 A1 A0 1 xxxx
Note: C3-C0 are the command op-code; A3, A2 are the NVMEM address; A1, A0 are the channel address.
7.8. BASIC OPERATION This chapter describes the sequences of commands to send to the WMS7202 and how to use the different features.
7.8.1 Sending a Command 1. Take the chip out of SLEEP mode. 2. Check that the write protect is set correctly if writing to NVMEM. 3. Check that R/B is HIGH before issuing command. 4. Pull the CS pin LOW before sending data to the device.
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WMS7202
5. 24 clock pulses are sent for each command. SDI must be valid on the rising edge of the clock, SDO is valid on the falling edge of the clock or CS . 6. Take CS HIGH after the command has completed. 7. If command 2, 4, 5, 6 or 7 is sent, wait for the R/B pin to go HIGH before sending the next command.
7.8.2 Wake Up/Sleep/Power Commands The chip is in SLEEP mode after: * * * VDD is applied A Power on Reset command is sent A SLEEP command is sent
Before any operations can be performed the WAKE UP command must be sent. When a SLEEP command is sent, the chip retains its resistor settings as long as the chip is powered up but cannot accept any other commands than a WAKE UP command. TABLE 6 - POWER RELATED COMMANDS Inst. No. 11 10 13 1 Command Name: Wake Up Sleep Power on Reset NOP Command Byte 0001xxxx 1000xxxx 1001xxxx 0000xxxx Data Byte 1 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx Data Byte 2 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx Comment Wake Up entire chip Send chip into power save mode Reset Chip Dummy instruction
The commands above control the entire chip. There is no way to independently power on or off individual potentiometers.
7.8.3 Write to Tap Register (TR) The microcontroller can write a value directly into the tap register or send an increment or decrement command to control the tap register. Alternatively, the contents of an NVMEM location can be written to the tap register. The only way to change the output buffer mode is to write the desired value of bit D8 into an NVMEM location and then load the corresponding NVMEM location into the tap register.
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WMS7202
TABLE 7 - WRITING TO THE TAP REGISTERS Inst. No. 3 Comman d Name: Write to Tap Register Up Down Load Tap Register Command Byte 0100 x x A1 A0 Data Byte 1 xxxxxxxx Data Byte 2 D7 D6 D5 D4 D3 D2 D1 D0 Comment Writes a value to the tap register of the selected channel Increment tap register value by one Decrement tap register value by one Load the selected NVMEM location into the tap register
8 9 6
0111 1111
x x
x A1 A0 x A1 A0
xxxxxxxx xxxxxxxx xxxxxxxx
xxxxxxxx xxxxxxxx xxxxxxxx
1 0 1 1 A3 A2 A1 A0
7.8.4 Programming Non-Volatile Memory (NVMEM) The value stored in the NVMEM location is 9 bits, the 8 bits (D7-D0) of the tap register plus 1 bit (D8) of the output buffer mode. The NVMEM position must be erased before writing to it. There are two ways to program a value into NVMEM. Write a value directly from the microcontroller Load the current potentiometer setting into NVMEM. TABLE 8 - PROGRAMMING NVMEM Inst. No 12 Command Name Erase NVMEM Program NVMEM Program NVMEM with Tap Register Command Byte 1 1 0 1 A3 A2 A1 A0 Data Byte 1 xxxxxxxx Data Byte 2 x x x x x x x x Comment Erases the 9 bit word pointed to by A3, A2, A1 and A0. Writes a value to the selected NVMEM register of the selected channel Takes the current potentiometer settings and saves in the selected NVMEM location.
5
0 0 1 0 A3 A2 A1 A0
x x x x x x x D8
D7 D6 D5 D4 D3 D2 D1 D0
7
0 0 1 1 A3 A2 A1 A0
xxxxxxxx
x
x
x
x
x
x
x
x
For programming NVMEM, the following sequence must be followed: 1. Erase word at NVMEM location 2. Program word at NVMEM location
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WMS7202
7.8.5 Reading Tap Registers and NVMEM Locations The contents of the tap register for any channel or any NVMEM location can be read back through the SDO pin. When a command is sent, the data is clocked out on the falling edge of the clock. Since daisy-chain operation requires data from one command to be clocked out when the next command arrives, any read command must be followed by another command to get the correct data on the SDO pin. TABLE 9 - READING THE TAP REGISTERS Inst. No. 4 Command Name: Read NVMEM Read Tap Register NOP to Read Register Command Byte 1 0 1 0 A3 A2 A1 A0 Data Byte 1 xxxxxxxx Data Byte 2 x x x x x x x x Comment Read the value of the selected NVMEM location Read the value of the selected tap register Output data to SDO pin
2 1
1100 0000
x x
x A1 A0 x x x
xxxxxxxx x x x x x x x D8
x
x
x
x
x
x
x
x
D7 D6 D5 D4 D3 D2 D1 D0
To read the contents of either the tap register or a NVMEM location, the following sequence must be followed. 1. Send the desired read command (#2 or #4) to select the register to read 2. Send another command such as NOP and read the SDO pin on the falling edge of the clock. The other command could be any command, but to make sure that the chip does not change anything, send either another Read command or a NOP command (#1).
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Publication Release Date: January 2003 Revision 1.1
WMS7202
8. TIMING DIAGRAMS
CLK tCYC tLEAD CS tDSU SDI tLAC SDO tRSU MSB MSB tPD LSB tST tSV tWPSU WP tWPH tDH LSB tLRL tWL tWH tLAG tCS
R/B
FIGURE 6 - WMS7202 TIMING DIAGRAM
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WMS7202
TABLE 10 - TIMING PARAMETERS PARAMETER SPI Clock Cycle Time SPI Clock HIGH Time SPI Clock LOW Time Lead Time Lag Time SDI Setup Time SDI Hold Time
CS to SDO - SPI Line Acquire CS to SDO - SPI Line Release
SYMBOL tCYC tWH tWL tLEAD tLAG tDSU tDH tLAC tLRL tPD tRSU tSV tCS tST tWPSU tWPH
MIN. 100 50 50 100 100 20 20 5 5 1 500
MAX.
UNIT ns ns ns ns ns ns ns ns ns ns ns
CLK to SDO Propagation Delay R/B Rise to CS Fall Store to NVMEM Save Time
CS Deselect Time
2 600 0.1 10 10
ms ns ms ns ns
Startup Time
WP Setup Time WP Hold Time
Note: The interface timing characteristics apply to all parts but are guaranteed by design and not subject to production test.
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Publication Release Date: January 2003 Revision 1.1
WMS7202
9. ABSOLUTE MAXIMUM RATINGS
TABLE 11 - ABSOLUTE MAXIMUM RATINGS Condition Junction temperature Storage temperature Voltage applied to any pad Vdd - Vss 150C -65 to +150C (Vss - 0.3V) to (VDD + 0.3V) -0.3 to 7.0V Value
Note: Exposure to conditions beyond those listed under: Absolute Maximum Ratings, may adversely affect the life and reliability of the device.
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WMS7202
10. ELECTRICAL CHARACTERISTICS
TABLE 12 - ELECTRICAL CHARACTERISTICS
All Parameters apply across specified operating ranges unless noted (VDD: 2.7V~5.5V; Temp: -40C~85C) Typical values: VDD=5V and T=25C
PARAMETER Rheostat Mode Nominal Resistance Different Non Linearity Integral Non Linearity Rheostat Tempco1 Wiper Resistance2
SYMBOL R DNL INL RAB/T RW
MIN. -20 -1 -1
TYP
MAX. +20 +1 +1
UNITS % LSB LSB ppm/ C
CONDITIONS T=25C, VW open
0.3 0.5 500 50 80
100 120
Bits LSB LSB ppm/ C LSB LSB V pF pF MHz KHz KHz uS
VDD=5V, I=VDD/RTotal VDD=2.7V, I=VDD/RTotal
Potentiometer Mode Resolution1 Different Non Linearity2 Integral Non Linearity2 Potentiometer Tempco1 Full Scale Error Zero Scale Error Resistor Terminal Voltage Range1 Terminal Capacitance1 Wiper Capacitance1 Dynamic Characteristics1
N DNL INL Vw/T VFSE VZSE VA,VB,VW CA, CB
8 -1 -1 +20 -1 0 VSS 30 30 1.5 300 200 80
+1 +1
Code = 80h Code = Full Scale Code = Zero Scale
0 1 VDD
BW10K Bandwidth -3dB Settling Time to 1 LSB BW50K BW100K TS 3
VDD=5V, VB=VSS
Code = Full Scale
100
Code = 80h CL=30pf VDD=5.5V=VA, VB=VSS VO=1/2 scale VA=2.5V, VDD=5V, f=1kHz, VIN=1VRMS
Analog Output (Buffer enabled) Amp Output Current2 IOUT Amp Output Resistance2 Rout Total Harmonic Distortion1 Digital Inputs/Outputs Input High Voltage Input Low Voltage Output Low Voltage Input Leakage Current THD VIH VIL VOL ILI
1
10 0.08
mA % V V V uA
0.7VDD 0.3VDD 0.4 +1
-1
IOL=2mA CS =VDD,Vin=Vss
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Publication Release Date: January 2003 Revision 1.1
WMS7202
~ VDD CS =VDD,Vin=VSS ~ VDD VDD=5V, fc = 1Mhz Code = 80h VDD=5V, fc = 1Mhz Code = 80h
Output Leakage Current Input Capacitance1 Output Capacitance1 Power Requirements Operating Voltage1 Operating Current Operating Current
ILo CIN COUT VDD IDDR IDDW ISA
-1 25 25 2.7 1 1 0.5 0.1
+1
uA pF pF
5.5 1.8 2 1 1 1
V mA mA mA uA LSB/V All ops except NVMEM program During Nonvolatile memory program Buffer is active, , no load Buffer is inactive, Power Down, No load VDD=5V10%, Code=80h
Standby Current
ISB2 PSRR
Power Supply Rejection Ratio
Note: 1. Not subject to production test; 2. Only on Final Test; 3. VDD = +2.7V to 5.5V, VSS = 0V, T = 25C, unless otherwise noted.
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WMS7202
10.1 TEST CIRCUITS
VA V+ VW
V+ = VDD 1LSB= V+/255 V+ VMS*
VA VW
V+ = VDD 10% PSRR(dB) = 20LOG( VMS ) VDD PSS(%/%) = VMS VDD
VB WMS7202
*Assume infinite input impedance
VB WMS7202
VMS*
*Assume infinite input impedance
Potentiometer divider nonlinearity error test circuit (INL, DNL) No Connection WMS7202 VA VW VB VMS * IW
Power supply sensitivity test circuit (PSS, PSRR)
VA W
WMS7202 VW
VB +5V VOUT
~
VIN
*Assume infinite input impedance
2.5V DC Offset Capacitance test circuit
Resistor position nonlinearity error test circuit (Rheostat Operation: R-INL, R-DNL) VMS * VA VW VB WMS7202 IW = V /RTotal DD IW
WMS7202 +5V VA VIN OFFSET GND 2.5V DC
~
VW VOUT VB
RW = V /IW MS
*Assume infinite input impedance
Wiper resistance test circuit
Gain vs. frequency test circuit FIGURE 7 - TEST CIRCUITS
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Publication Release Date: January 2003 Revision 1.1
WMS7202
11. TYPICAL APPLICATION CIRCUIT
RA RB
Vin WMS7202
_ OP AMP +
VOUT
VOUT = - VIN RA =
RB RA
RB =
RABD 256
RAB(256 - D) , 256
RAB = Total resistance of potentiometer D = Wiper setting for WMS7202
FIGURE 8 - PROGRAMMABLE INVERTING GAIN AMPLIFIER USING THE WMS7202
VIN
+
OP _ AMP
VOUT
RA
RB
WMS7202 VOUT = VIN (1+ RA =
RB ) RA
RAB(256 - D) RABD , RB = 256 256
RAB = Total resistance of potentiometer D = Wiper setting for WMS7202 FIGURE 9 - PROGRAMMABLE NON-INVERTING GAIN AMPLIFIER USING THE WMS7202
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WMS7202
V+
I = 32mA VREFH VREF = 5.0v WMS7202
GND FIGURE 10 - WMS7202 TRIMMING VOLTAGE REFERENCE
WMS7202P-14
AUDIO TONE CONTROL EXAMPLE
FIGURE 11 - WMS7202 AUDIO TONE CONTROL
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Publication Release Date: January 2003 Revision 1.1
1
+
CS CLK SDI WP GND R/B VA2
VDD SDO VA1 VW1 VB1 VB2 VW2
2
-
1 2 3 4 5 6 7
U1
U2 6
14 13 12 11 10 9 8
3
8
WMS7202
11 Vin 10 R1 1/2 WMS7202 CS\ CLK SDI WP\ CONTROL 1 2 3 4 56 12 7
8 9 R2 1/2 WMS7202 14 13 VDD SDO R/B\
8 1 + 3 2
6
Vout
PROGRAMMABLE LOW-PASS FILTER
FIGURE 12 - PROGRAMMABLE LOW-PASS FILTER
- 24 -
WMS7202
11.1. LAYOUT CONSIDERATIONS A 0.1F bypass capacitor as close as possible to the VDD pin is recommended for best performance. Often this can be done by placing the surface mount capacitor on the bottom side of the PC board, directly between the VDD and VSS pins. Care should be taken to separate the analog and digital traces. Sensitive traces should not run under the device or close to the bypass capacitors. A dedicated plane for analog ground helps in reducing ground noise for sensitive analog signals.
FIGURE 13 - WMS7202 LAYOUT
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Publication Release Date: January 2003 Revision 1.1
WMS7202
12. PACKAGE DRAWINGS AND DEMINSIONS
14 8
E
E1
1
7
D eA
BASE PLANE A1
SEATING PLANE
L
e1
B
B1
SYMBOL
DIMENSION (MM) MIN. NOM MAX.
DIMENSION (INCH) MIN. 0.015 NOM MAX.
A1 B B1 c D E E1 e1 L eA
0.381 0.406 1.397 0.457 1.524 0.25 18.80 7.62 6.25 19.05 7.925 6.35 2.54BSC 2.2921 8.382 8.89 9.398 19.30 8.230 6.45 0.508 1.651
0.016 0.055
0.018 0.060 0.010
0.020 0.065
0.740 0.300 0.246
0.750 0.312 0.250 0.1 BSC.
0.760 0.324 0.254
0.115 0.330 0.350 0.370
FIGURE 14 - 14L PDIP - 300MIL
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WMS7202
1
8
c
E
HE
L
1
D
7
0.25
O
A Y SEATING PLANE b SYMBOL e A1 DIMENSION (MM) MIN. A A1 b c E D e HE Y L 0 0.40 0 1.35 0.10 0.33 0.19 3.80 8.55 MAX. 1.75 0.25 0.51 0.25 4.00 8.75 DIMENSION (INCH) MIN. 0.053 0.004 0.013 0.008 0.150 0.337 MAX. 0.069 0.010 0.020 0.010 0.157 0.344 GAUGE PLANE
1.27 BSC. 5.80 6.20 0.10 1.27 8
0.050 BSC. 0.228 0.244 0.004 0.016 0 0.050 8
FIGURE 15 - 14L SOIC - 150MIL
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Publication Release Date: January 2003 Revision 1.1
WMS7202
E
e b
D A A
A Y SEATING PLANE
DIMENSION (INCH) MAX 1.20 0.05 0.80 0.50 0.90 0.60 6.40 BSC 4.30 0.19 4.90 5.00 0.076 0.65 BSC 0 8 0 4.40 4.50 0.30 5.10 0.169 0.007 0.193 0.197 0.006 0.026 BSC 8 0.15 1.05 0.75 0.002 0.031 0.020 0.035 0.024 0.252 BSC 0.173 0.177 0.012 0.201 MIN NOM MAX 0.043 0.006 0.041 0.030
DIMENSION (MM) SYMBOL A A1 A2 L E HE b D/mm Y e e1 MIN. NOM
FIGURE 16 - 14L TSSOP - 4.4MM
- 28 -
WMS7202
13. ORDERING INFORMATION
Winbond's WinPot Part Number Description: WMS72 XX XXX X
Winbond WinPot Products Features: * * * 01: Single channel with SPI Interface 02: Dual channels with SPI Interface 04: Quad channels with SPI Interface
End-to-end Resistance: * * * 010: 10K 050: 50K 100: 100K
Package Index: * T: TSSOP * S: SOIC * P: PDIP
For the latest product information, access Winbond's worldwide website at http://www.winbond-usa.com
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Publication Release Date: January 2003 Revision 1.1
WMS7202
14. VERSION HISTORY
VERSION 1.0 1.1 DATE June 2002 Jan. 2003 PAGE All Initial issue Correct typos, add Inst No. to tables, add values to Specification DESCRIPTION
The contents of this document are provided only as a guide for the applications of Winbond products. Winbond makes no representation or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to discontinue or make changes to specifications and product descriptions at any time without notice. No license, whether express or implied, to any intellectual property or other right of Winbond or others is granted by this publication. Except as set forth in Winbond's Standard Terms and Conditions of Sale, Winbond assumes no liability whatsoever and disclaims any express or implied warranty of merchantability, fitness for a particular purpose or infringement of any Intellectual property. Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipments intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental injury could occur.
Headquarters
No. 4, Creation Rd. III Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441797 http://www.winbond-usa.com/
Winbond Electronics (Shanghai) Ltd.
27F, 299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62356998
Taipei Office
9F, No. 480, Pueiguang Rd. Neihu District Taipei, 114 Taiwan TEL: 886-2-81777168 FAX: 886-2-87153579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG. 3-7-18 Shinyokohama Kohokuku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners. This product incorporates SuperFlash(R) technology licensed From SST
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